Conventional mobile devices increasingly serve many functions such as cellular phone calling, Internet or wi-fi access, general purpose graphical applications, video and/or image processing. Each of these applications use system resources differently. Future devices are expected to integrate even more features. Such new features will likely add new types of resource requirements and memory patterns.
Application-specific integrated circuits include special-purpose hardware units to accelerate critical functions within such hybrid systems. Such hardware units coexist on the same integrated circuit and share a common pool of systems resources. A host processor typically acts as a resource manager by allocating memory for each unit, reclaiming unused or free memory, providing security to prevent unauthorized access to memory contents, and managing power usage. Depending on the overall system requirements, the resource manager can also operate as a collection of host processors.
Conventional operating systems use virtual memory to provide a single interface to each program. Such an approach provides the illusion to the client of having a contiguous block of memory addresses. However, the addresses are fragmented in a physical storage device (i.e., DRAM, FLASH card, or an external storage devices, etc.). Virtual memory systems translate virtual memory addresses to physical memory accesses via virtual to physical table lookups.
Modern virtual memory systems are sometimes separate virtual and physical memory into blocks of a fixed or variable size called pages. When a program accesses a new virtual page, the host processor accesses the page table to translate the virtual page number (VPN) to a physical page number (PPN) to construct the physical address and access the correct location in memory. Page-table lookups are time-intensive operations. Modern processors provide a cache of virtual to physical translations for the host-processor. This cache is sometimes referred to as an address translation cache or translation look-aside buffer (TLB).
Clients also need to access physical memory, either to perform specific functions or to execute proxy transfers for the host (i.e., Direct Memory Access (DMA)). If clients access physical storage through virtual memory, such clients need to access the TLB directly or to keep shadow copies of the TLB entires locally to keep the mapping tables of the various clients consistent. In both cases, clients use a page table lookup operation to find new pages or pages no longer found in the TLB. Communication occurs from the host to the clients when the host changes virtual to physical translations.
However, clients often have real-time deadlines that must be met to operate properly. These deadlines are especially important in digital image and video processing, medical devices, aeronautical systems, automobiles or other mechanical control systems where real-time deadlines are critical. Missing a deadline in these cases can lead to image corruption, data inaccuracies, or other system errors with disastrous consequences. Memory space used by these devices does not generally fit in the TLB exclusively (i.e., page table lookups are needed when page-table entries are not found in the buffer).
Clients with real-time constraints typically cannot leverage TLBs because a page-table access is too expensive and unpredictable. Too many page table lookups can stall the client, potentially causing a missed deadline. Modern real-time systems attempt to solve this problem by supporting physical-only memory accesses exclusively or splitting physical storage between physical-only access for clients and virtual-only memory access for general-purpose applications.
The first approach drops key benefits of virtual memory. The second approach creates a sub-optimal allocation of system storage because the division is static and cannot easily adjust if the system migrates from running general-purpose applications to real-time applications or visa versa.
It would be desirable to implement a host processor to provide the benefits of virtual memory while allowing real-time clients to meet performance deadlines.